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Timer Template Klasse

timer1_templ.h.html

   1:  /********************************************************************
   2:  *     Copyright (C) 2011  Philipp Klostermann
   3:  *
   4:  *    timer1_templ.h
   5:  *
   6:  *    This program is free software: you can redistribute it and/or modify
   7:  *    it under the terms of the GNU General Public License as published by
   8:  *    the Free Software Foundation, either version 3 of the License, or
   9:  *    any later version.
  10:  *
  11:  *    This program is distributed in the hope that it will be useful,
  12:  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13:  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14:  *    GNU General Public License for more details.
  15:  *
  16:  *    You should have received a copy of the GNU General Public License
  17:  *    along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18:  *
  19:  *	Email the autor: philipp.klostermann@pksl.de
  20:  *	Address: 
  21:  *	 Philipp Klostermann
  22:  *	 Luchert 45
  23:  *	 56593 Horhausen
  24:  *	 Germany
  25:  *********************************************************************/
  26:  
  27:  #ifndef __TIMER1_H_INCLUDED__
  28:  #define __TIMER1_H_INCLUDED__
  29:  
  30:  /* Clock select bits: */
  31:  
  32:  #define TIMER1_CS_STOP              (0 << 8)
  33:  #define TIMER1_CS_BY_1              (1 << 8)
  34:  #define TIMER1_CS_BY_8              (2 << 8)
  35:  #define TIMER1_CS_BY_64             (3 << 8)
  36:  #define TIMER1_CS_BY_256            (4 << 8)
  37:  #define TIMER1_CS_T1_PIN_FALLING    (6 << 8)
  38:  #define TIMER1_CS_T1_PIN_RISING     (7 << 8)
  39:  
  40:  /* Compare Outpt Mode Bits:
  41:  COM     non-PWM                         fast PWM                                                        phase correct PWM
  42:  0       OC1A/B disconnected             OC1A/B disconnected                                             OC1A/B disconnected
  43:  1       Toggle OC1A/B on compare match  WGM13:0 != 15: OC1A/B disconnected                              WGM13:0 != 9 or 14: OC0A/B disconnected
  44:                                          WGM13:0 == 15: Toggle OC1A on compare match, OC1B disconnected  WGM13:0 == 9 or 14: Toggle OC1A on compare match, OC1B disconnected
  45:  2       Clear OC1A/B on compare match   Clear OC1A/B on compare match, set OC1A/B at BOTTOM             Clear OC1A/B on compare match when up-counting, Set OC1A/B on compare match when down-counting
  46:  3       Set OC1A/B on compare match     Set OC1A/B on compare match, Clear OC1A/B at BOTTOM             Set OC1A/B on compare match when up-counting, Clear OC1A/B on compare match when down-counting
  47:  
  48:  */
  49:  
  50:  #define TIMER1_COM_OC1AB_DISCONNECTED                               0
  51:  #define TIMER1_COM_NON_PWM_TOGGLE_OC1A_ON_CM                        (1 << COM1A0)
  52:  #define TIMER1_COM_NON_PWM_CLEAR_OC1A_ON_CM                         (2 << COM1A0)
  53:  #define TIMER1_COM_NON_PWM_SET_OC1A_ON_CM                           (3 << COM1A0)
  54:  #define TIMER1_COM_FAST_PWM_TOP_OCR1A_TOGGLE_OC1A_ON_CM             (1 << COM1A0)
  55:  #define TIMER1_COM_FAST_PWM_CLEAR_OC1A_ON_CM_SET_OC1A_AT_BOTTOM     (2 << COM1A0)
  56:  #define TIMER1_COM_FAST_PWM_SET_OC1A_ON_CM_CLEAR_OC1A_AT_BOTTOM     (3 << COM1A0)
  57:  #define TIMER1_COM_PHASE_WGM_EQ_9_OR_14_TOGGLE_OC1A_ON_CM           (1 << COM1A0)
  58:  #define TIMER1_COM_PHASE_PWM_CL_OC1A_ON_CM_UP_ST_OC1A_ON_CM_DOWN    (2 << COM1A0)
  59:  #define TIMER1_COM_PHASE_PWM_ST_OC1A_ON_CM_UP_CL_OC1A_ON_CM_DOWN    (3 << COM1A0)
  60:  
  61:  #define TIMER1_COM_NON_PWM_TOGGLE_OC1B_ON_CM                        (1 << COM1B0)
  62:  #define TIMER1_COM_NON_PWM_CLEAR_OC1B_ON_CM                         (2 << COM1B0)
  63:  #define TIMER1_COM_NON_PWM_SET_OC1B_ON_CM                           (3 << COM1B0)
  64:  #define TIMER1_COM_FAST_PWM_TOP_OCR1A_TOGGLE_OC1B_ON_CM             (1 << COM1B0)
  65:  #define TIMER1_COM_FAST_PWM_SET_OC1AB_ON_CM_CLEAR_OC1B_AT_BOTTOM    (3 << COM1B0)
  66:  #define TIMER1_COM_PHASE_PWM_CL_OC1AB_ON_CM_UP_ST_OC1B_ON_CM_DOWN   (2 << COM1B0)
  67:  #define TIMER1_COM_PHASE_PWM_ST_OC1AB_ON_CM_UP_CL_OC1B_ON_CM_DOWN   (3 << COM1B0)
  68:  
  69:  #define TIMER1_NORMAL                                           0 
  70:  #define TIMER1_NORMAL_TOGGLE_OC1A_ON_CM                         (1 << COM1A0)
  71:  #define TIMER1_NORMAL_TOGGLE_OC1B_ON_CM                         (1 << COM1B0)
  72:  #define TIMER1_NORMAL_CLEAR_OC1A_ON_CM                          (2 << COM1A0)
  73:  #define TIMER1_NORMAL_CLEAR_OC1B_ON_CM                          (2 << COM1B0)
  74:  #define TIMER1_NORMAL_SET_OC1A_ON_CM                            (3 << COM1A0)
  75:  #define TIMER1_NORMAL_SET_OC1B_ON_CM                            (3 << COM1B0)
  76:  #define TIMER1_PHASE_PWM_8                                      (1 << WGM10)
  77:  #define TIMER1_PHASE_PWM_8_CLR_OC1A_UP_SET_OC1A_DWN             (1 << WGM10) | (2 << COM1A0)
  78:  #define TIMER1_PHASE_PWM_8_CLR_OC1B_UP_SET_OC1B_DWN             (1 << WGM10) | (2 << COM1B0)
  79:  #define TIMER1_PHASE_PWM_8_SET_OC1A_UP_CLR_OC1A_DWN             (1 << WGM10) | (3 << COM1A0)
  80:  #define TIMER1_PHASE_PWM_8_SET_OC1B_UP_CLR_OC1B_DWN             (1 << WGM10) | (3 << COM1B0)
  81:  #define TIMER1_PHASE_PWM_9                                      (2 << WGM10)
  82:  #define TIMER1_PHASE_PWM_9_CLR_OC1A_UP_SET_OC1A_DWN             (2 << WGM10) | (2 << COM1A0)
  83:  #define TIMER1_PHASE_PWM_9_CLR_OC1B_UP_SET_OC1B_DWN             (2 << WGM10) | (2 << COM1B0)
  84:  #define TIMER1_PHASE_PWM_9_SET_OC1A_UP_CLR_OC1A_DWN             (2 << WGM10) | (3 << COM1A0)
  85:  #define TIMER1_PHASE_PWM_9_SET_OC1B_UP_CLR_OC1B_DWN             (2 << WGM10) | (3 << COM1B0)
  86:  #define TIMER1_PHASE_PWM_10                                     (3 << WGM10)
  87:  #define TIMER1_PHASE_PWM_10_CLR_OC1A_UP_SET_OC1A_DWN            (3 << WGM10) | (2 << COM1A0)
  88:  #define TIMER1_PHASE_PWM_10_CLR_OC1B_UP_SET_OC1B_DWN            (3 << WGM10) | (2 << COM1B0)
  89:  #define TIMER1_PHASE_PWM_10_SET_OC1A_UP_CLR_OC1A_DWN            (3 << WGM10) | (2 << COM1A0)
  90:  #define TIMER1_PHASE_PWM_10_SET_OC1B_UP_CLR_OC1B_DWN            (3 << WGM10) | (2 << COM1B0)
  91:  #define TIMER1_CTC_TOP_OCRA                                     (0 << WGM10)                 | ((1 << WGM12) << 8)
  92:  #define TIMER1_CTC_TOP_OCRA_TOGGLE_OC1B_CM                      (0 << WGM10) | (1 << COM1B0) | ((1 << WGM12) << 8)
  93:  #define TIMER1_CTC_TOP_OCRA_CLR_OC1B_CM                         (0 << WGM10) | (2 << COM1B0) | ((1 << WGM12) << 8)
  94:  #define TIMER1_CTC_TOP_OCRA_SET_OC1B_CM                         (0 << WGM10) | (3 << COM1B0) | ((1 << WGM12) << 8)
  95:  #define TIMER1_FAST_PWM_8                                       (1 << WGM10)                 | ((1 << WGM12) << 8)
  96:  #define TIMER1_FAST_PWM_8_CLR_OC1A_CM_SET_OC1A_BOTT             (1 << WGM10) | (2 << COM1A0) | ((1 << WGM12) << 8)
  97:  #define TIMER1_FAST_PWM_8_CLR_OC1B_CM_SET_OC1B_BOTT             (1 << WGM10) | (2 << COM1B0) | ((1 << WGM12) << 8)
  98:  #define TIMER1_FAST_PWM_8_SET_OC1A_CM_CLR_OC1A_BOTT             (1 << WGM10) | (3 << COM1A0) | ((1 << WGM12) << 8)
  99:  #define TIMER1_FAST_PWM_8_SET_OC1B_CM_CLR_OC1B_BOTT             (1 << WGM10) | (3 << COM1B0) | ((1 << WGM12) << 8)
 100:  #define TIMER1_FAST_PWM_9                                       (2 << WGM10)                 | ((1 << WGM12) << 8)
 101:  #define TIMER1_FAST_PWM_9_CLR_OC1A_CM_SET_OC1A_BOTT             (2 << WGM10) | (2 << COM1A0) | ((1 << WGM12) << 8)
 102:  #define TIMER1_FAST_PWM_9_CLR_OC1B_CM_SET_OC1B_BOTT             (2 << WGM10) | (2 << COM1B0) | ((1 << WGM12) << 8)
 103:  #define TIMER1_FAST_PWM_9_SET_OC1A_CM_CLR_OC1A_BOTT             (2 << WGM10) | (3 << COM1A0) | ((1 << WGM12) << 8)
 104:  #define TIMER1_FAST_PWM_9_SET_OC1B_CM_CLR_OC1B_BOTT             (2 << WGM10) | (3 << COM1B0) | ((1 << WGM12) << 8)
 105:  #define TIMER1_FAST_PWM_10                                      (3 << WGM10)                 | ((1 << WGM12) << 8)
 106:  #define TIMER1_FAST_PWM_10_CLR_OC1A_CM_SET_OC1A_BOTT            (3 << WGM10) | (2 << COM1A0) | ((1 << WGM12) << 8)
 107:  #define TIMER1_FAST_PWM_10_CLR_OC1B_CM_SET_OC1B_BOTT            (3 << WGM10) | (2 << COM1B0) | ((1 << WGM12) << 8)
 108:  #define TIMER1_FAST_PWM_10_SET_OC1A_CM_CLR_OC1A_BOTT            (3 << WGM10) | (3 << COM1A0) | ((1 << WGM12) << 8)
 109:  #define TIMER1_FAST_PWM_10_SET_OC1B_CM_CLR_OC1B_BOTT            (3 << WGM10) | (3 << COM1B0) | ((1 << WGM12) << 8)
 110:  #define TIMER1_PHASE_FREQ_PWM_TOP_ICR1                          (0 << WGM10)                 | ((2 << WGM12) << 8)
 111:  #define TIMER1_PHASE_FREQ_PWM_TOP_ICR1_CLR_OC1A_UP_SET_OC1A_DWN (0 << WGM10) | (2 << COM1A0) | ((2 << WGM12) << 8)
 112:  #define TIMER1_PHASE_FREQ_PWM_TOP_ICR1_CLR_OC1B_UP_SET_OC1B_DWN (0 << WGM10) | (2 << COM1B0) | ((2 << WGM12) << 8)
 113:  #define TIMER1_PHASE_FREQ_PWM_TOP_ICR1_SET_OC1A_UP_CLR_OC1A_DWN (0 << WGM10) | (3 << COM1A0) | ((2 << WGM12) << 8)
 114:  #define TIMER1_PHASE_FREQ_PWM_TOP_ICR1_SET_OC1B_UP_CLR_OC1B_DWN (0 << WGM10) | (3 << COM1B0) | ((2 << WGM12) << 8)
 115:  // ...
 116:  #define TIMER1_CTC_TOP_ICR1                                     (0 << WGM10)                 | ((3 << WGM12) << 8)
 117:  
 118:  /*
 119:  WGM  Mode                            TOP     upd OCR1x   TOV flag set on
 120:   0   Normal                          0xFFFF  Immediate   MAX
 121:   1   PWM, phase correct 8 bit        0x00FF  TOP         BOTTOM
 122:   2   PWM, phase correct 9 bit        0x01FF  TOP         BOTTOM
 123:   3   PWM, phase correct 10 bit       0x03FF  TOP         BOTTOM
 124:   4   CTC                             OCRA    Immediate   MAX
 125:   5   Fast PWM 8 bit                  0x00FF  BOTTOM      TOP
 126:   6   Fast PWM 9 bit                  0x01FF  BOTTOM      TOP
 127:   7   Fast PWM 10 bit                 0x03FF  BOTTOM      TOP
 128:   8   PWM, Phase & Frequency Correct  ICR1    BOTTOM      BOTTOM
 129:   9   PWM, Phase & Frequency Correct  OCR1A   BOTTOM      BOTTOM
 130:  10   PWM, phase correct              ICR1    TOP         BOTTOM
 131:  11   PWM, phase correct              OCR1A   BOTTOM      BOTTOM
 132:  12   CTC                             ICR1    Immediate   MAX
 133:  13   reserved
 134:  14   Fast PWM                        ICR1    BOTTOM      TOP
 135:  15   Fast PWM                        OCR1A   BOTTOM      TOP
 136:  */
 137:  
 138:  #define TIMER1_WGM_NORMAL                                        0
 139:  #define TIMER1_WGM_PWM_PHASE_CORRECT_8_BIT                       1
 140:  #define TIMER1_WGM_PWM_PHASE_CORRECT_9_BIT                       2
 141:  #define TIMER1_WGM_PWM_PHASE_CORRECT_10_BIT                      3
 142:  #define TIMER1_WGM_CTC_TOP_OCRA1                                 4
 143:  #define TIMER1_WGM_FAST_PWM_8_BIT                                5
 144:  #define TIMER1_WGM_FAST_PWM_9_BIT                                6
 145:  #define TIMER1_WGM_FAST_PWM_10_BIT                               7
 146:  #define TIMER1_WGM_PWM_PHASE_N_FREQUENCY_CORRECT_TOP_ICR1        8
 147:  #define TIMER1_WGM_PWM_PHASE_N_FREQUENCY_CORRECT_TOP_OCRA1       9
 148:  #define TIMER1_WGM_PWM_PHASE_CORRECT_TOP_ICR1                   10
 149:  #define TIMER1_WGM_PWM_PHASE_CORRECT_TOP_OCR1A                  11
 150:  #define TIMER1_WGM_CTC_TOP_ICR1                                 12
 151:  #define TIMER1_WGM_FAST_PWM_TOP_ICR1                            14
 152:  #define TIMER1_WGM_FAST_PWM_TOP_OCR1A                           15
 153:  
 154:  template<uint16_t CTimer1Tmpltccr, 
 155:  		uint8_t CTimer1Tmpltimsk, 
 156:  		bool CTimer1TmplbStart,
 157:  		int16_t CTimer1TmplOcr1A,
 158:  		int16_t CTimer1TmplOcr1B,
 159:  		int16_t CTimer1TmplIcr1> 
 160:  	class CTimer1Tmpl
 161:  {
 162:  public:
 163:  	CTimer1Tmpl()
 164:  	{
 165:  		OCR1A = CTimer1TmplOcr1A;
 166:  		OCR1B = CTimer1TmplOcr1B;
 167:  		ICR1 = CTimer1TmplIcr1;
 168:  		TCCR1A = (CTimer1Tmpltccr & 0xff);
 169:  		if (CTimer1TmplbStart)
 170:  		{
 171:  			TCCR1B = (CTimer1Tmpltccr >> 8);
 172:  		}
 173:  		else
 174:  		{
 175:  			TCCR1B = (CTimer1Tmpltccr >> 8) & (~(7 << CS10));
 176:  		}
 177:  #ifdef __AVR_ATmega88__
 178:  		TIMSK1 = CTimer1Tmpltimsk;
 179:  #else

 180:  		TIMSK = CTimer1Tmpltimsk;
 181:  #endif

 182:  	}
 183:  	void Start()
 184:  	{
 185:  		TCCR1B |= (((CTimer1Tmpltccr >> 8) & (7 << CS10)) << CS10);
 186:  	}
 187:  	void Stop()
 188:  	{
 189:  		TCCR1B &= ~(7 << CS10);
 190:  	}
 191:  };
 192:  
 193:  #endif // #ifndef __TIMER1_H_INCLUDED__